Homogeneous VLSI Structures for Finite Ring Computations1

This paper discusses the basic concepts, and presents some preliminary results, of an approach towards the development of homogeneous arrays for massively parallel VLSI computation of Digital Signal Processing algorithms. The generation of such arrays is made possible by computing over finite rings, rather than weighted magnitude systems, such as binary, and by performing the computations at the bit-level. The architectures are systolic, or semi-systolic, in that local communication between bit-level cells is preserved, in the main, with pipelining operating at the bit level. The homogeneity of the arrays results from the use of a single generic cell structure that allows a pipelined bit-level inner product step to be computed using only twice the silicon area of a pipelined full-adder, and operating at a slightly higher throughput rate. The cell can be used for implementing a wide variety of DSP algorithms, including coding and decoding between conventional systems and the finite rings used for the computations. Since the use of an inner product step processor requires only twice the area of a binary adder, the complexity normally associated with multiplication (compared to that for addition) has now been removed, without compromising array structure and throughput. This means that algorithms can now be chosen for their VLSI structure rather than reduction of complexity of multiplication. The paper illustrates this concept by considering the homogeneous array implementation of a 2-D radix-2 DFT computational element with twiddle factor multipliers, a structure normally implemented with an irregular architecture.